State machines (or finite state machines, as they are also called) can be defined as self-contained systems having a set of “states” and certain “transitions” between these states. They are often used in the design of digital circuits. There are a number of development tools on the market for implementing state machines in programmable logic (such as e.g. PLDs, CPLDs or FGPAs). State machines can be divided into two classes according to the type of result or, as the case may be, output they yield. On the one hand there are Moore state machines, whose output is simply a function of the current state. Mealy state machines, on the other hand, are characterized in that one or more outputs is/are a function of the current state and one or more inputs.
The usual approach in contemporary hardware design is, in a first step, to generate a VHDL code or a code in another hardware description language in order then, in a second step, to convert said code into a logic circuit using a synthesis tool. There are basically two options for generating the VHDL code: Firstly, it is possible to write the VHDL code by hand using a text editor for example. Secondly, it is possible to use a tool, specifically a graphical model with predefined syntax, which simplifies and automates the description of state machines and in addition results in a unique and syntactically error-free code. When using the aforementioned graphical input it is, however, necessary to use an additional code generator which converts the graphical model (or, as the case may be, the graphic) into VHDL code by interpreting the graphic.
If the first of the aforementioned possibilities is chosen and the VHDL code is programmed manually, this is more problematical, more complicated and time-consuming, and less convenient, and has the disadvantages that the VHDL code may not be unique and possibly not free of syntactical errors.
In order to avoid the aforementioned disadvantages and in the interests of improved clarity, the most common practice is therefore to use a graphic, in other words to opt for the second of the aforementioned possibilities.
A problem with the previous code generation based on a graphical input mode is to be seen in the fact that the generated code exhibits a lack of efficiency, since often unnecessarily many gates or, as the case may be, cells are generated and the clock frequency is low.
In order to overcome these disadvantages it is known in the prior art to use what is referred to as “one-hot coding”. With one-hot coding, each state is described by an individual bit in the state vector. Although in this type of coding a greater number of bits are used for coding the respective states, usually only the relevant bit in each case must be realized in code during the subsequent decoding. In practice, however, it has been found that nonetheless, in the customary method of describing state machines, all bits of the state vector must be realized in code (and not just the relevant bit in each case, as the one-hot coding approach actually proposes).
The existing prior art solutions therefore reveal themselves as deficient.